1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly it pertains to a semiconductor integrated circuit including merged transistors constituting a flip-flop circuit.
2. Description of the Prior Art
Hereinbelow, description will be made in connection with the accompanying drawings.
FIGS. 1 and 2 show a conventional semiconductor memory cell proposed in IEEE Journal of Solid State Circuits, October 1973. A memory cell of FIG. 1 is formed with a pair of inverter transistors Q.sub.3 and Q.sub.4 for holding memory, a pair of load transistors Q.sub.1 and Q.sub.2, and a pair of current source transistors Q.sub.5 and Q.sub.6. The collectors of the inverter transistors Q.sub.3 and Q.sub.4 are connected to the bases of the inverter transistors Q.sub.4 and Q.sub.3, respectively. This memory cell is achieved by the structure as shown in FIG. 2. In FIG. 2, a semiconductor wafer 10 is comprised of an n type semiconductor substrate 11 of a low resistivity and an n type epitaxial layer 12 of a relatively high resistivity grown thereon. In this n type layer 12, p type semiconductor regions 13, 14, 15, 16 and 17 of a relatively low resistivity are formed by relying on the selective diffusion technique. Furthermore, in the p type regions 14 and 16 are formed n type semiconductor regions 18 and 19 of a further low resistivity. Metal electrodes 20, 21, 22, 23, 24, 25 and 26 are formed on the respective semiconductor regions 13, 14, 15, 16, 17, 18 and 19. Another electrode 27 is formed on the lower surface of the semiconductor substrate 11. Pairs of the electrodes 21 and 26, and 23 and 25 are electrically connected through metal layers. The electrode 27 is used as the X address electrode, and the electrode 22 as the Y address electrode. The electrodes 20 and 24 are used as the read/write electrodes RW.sub.0 and RW.sub.1, respectively.
Now, the correlation between FIGS. 1 and 2 will be described. The semiconductor regions 12, 14 and 15 constitute the base, the collector and the emitter of the pnp type bipolar transistor Q.sub.1, respectively. The semiconductor regions 12, 16 and 15 constitute the base, the collector and the emitter of the pnp type bipolar transistor Q.sub.2, respectively. It will be seen that the emitter and the base regions of the pnp type bipolar transistors Q.sub.1 and Q.sub.2 are common with each other, and connected to the electrodes Y and X. The semiconductor regions 12, 16 and 19 constitute the emitter, the base and the collector regions of the npn bipolar transistor Q.sub.3, respectively, while the semiconductor regions 12, 14 and 18 constitute the emitter, the base and the collector regions of the npn transistor Q.sub.4, respectively. Here, the n.sup.+ type region 11 is considered as part of the n type region 11. The semiconductor regions 17, 12 and 16 constitute the emitter (or collector), the base and the collector (or emitter) regions of the pnp type transistor Q.sub.5, respectively, while the semiconductor regions 13, 12 and 14 constitute the collector (or emitter), the base and the emitter (or collector) regions of the pnp type transistor Q.sub.6, respectively. The p type collector region 14 of the pnp type transistor Q.sub.1 is connected to the n type collector region 19 of the npn type transistor Q.sub.3 through a metal lead, and similarly the p type collector region 16 of the pnp type transistor Q.sub.2 is connected to the n type collector region 18 of the npn type transistor Q.sub.4.
Such a conventional semiconductor memory cell is accompanied by the following drawbacks and inconveniences.
The collector loads for the inverter transistors Q.sub.3 and Q.sub.4 for holding the memory content are formed with bipolar transistors Q.sub.1 and Q.sub.2 of the lateral structure as shown in FIG. 2. Therefore, the switching speed of these transistors Q.sub.1 and Q.sub.2 cannot be made very high. Then, the maximum operation speed of this conventional memory cell is limited by the switching speed of the transistors Q.sub.1 and Q.sub.2.
Furthermore, the clocking for this memory cell should be achieved by applying power pulses to the Y address electrode Y. Thus, the power required for clocking is large.
In the above structure, the transistors Q.sub.1 and Q.sub.2 inject carriers into the base regions of the transistors Q.sub.4 and Q.sub.3. In the bipolar transistor of the lateral structure, it is very difficult to reduce the base width W.sub.B from the viewpoint of manufacture, and hence the carrier injection efficiency (equal to the common base current amplification factor) can not be made high. Namely, the leak component of carriers is large, and hence the power dissipation is large. Particularly, when the quantity of injected carriers becomes large, the potentials at the collectors 14 and 16 of the transistors Q.sub.1 and Q.sub.2 rise to cause the reverse injection from these collectors 14 and 16, and the pn-junction between the emitter 15 and the base 12 is forwardly and deeply biased. Thus, the effect of the base resistance becomes large, and the ratio of carriers escaping into the semiconductor substrate 11 increases. Therefore, the carrier injection efficiency .alpha. rapidly decreases as the injection current (the current injected from the Y address electrode Y) increases. There is the need of increasing the injection current to inject many carriers for reducing the charging and discharging time period for the parasitic capacitances at respective portions and for increasing the switching speed of the transistors Q.sub.1 and Q.sub.2. Here, power loss rapidly increases as the injection current is increased. Thus, there is difficulty in integrating the conventional memory cells with a high density.
FIGS. 3 and 4 show an example of the conventional semiconductor register cell. A register cell is formed with a master flip-flop MF and a slave flip-flop SF. Each of these flip-flops includes four transistors Q.sub.1 to Q.sub.4. Each of the inverter transistors Q.sub.3 and Q.sub.4 has two collectors, one of which is connected to the base of the other inverter transistor of the same flip-flop. The load transistors Q.sub.1 and Q.sub.2 also serve to inject carriers into the bases of the inverter transistors Q.sub.4 and Q.sub.3. Namely, the load transistor Q.sub.1 injects carriers into the base of the inverter transistor Q.sub.4 when the other inverter transistor Q.sub.3 is turned off.
A first clock pulse signal .phi..sub.1 is applied to the common emitter of the load transistors Q.sub.1 and Q.sub.2 of the master flip-flop MF, while a second clock pulse signal .phi..sub.2 in opposite phase to the first clock pulse signal .phi..sub.1 is applied to the common emitter of the load transistors Q.sub.1 and Q.sub.2 of the slave flip-flop SF. The second collectors of the inverter transistors Q.sub.3 and Q.sub.4 of the master flip-flop MF are connected to the first collectors of the inverter transistors Q.sub.3 and Q.sub.4 of the slave flip-flop SF through lines L.sub.1 and L.sub.2, respectively. The inputs to this register cell, e.g. the outputs of another register cell, are supplied to the bases of the inverter transistors Q.sub.4 and Q.sub.3 of the master flip-flop MF through lines L.sub.3 and L.sub.4, respectively. The outputs of this register cell, i.e. the signals at the second collectors of the inverter transistors Q.sub.3 and Q.sub.4 of the slave flip-flop SF, are supplied to the following register cell or other logic circuit portion through lines L.sub.5 and L.sub.6, respectively.
Since the operation of this register cell is well known, brief description thereof will be made hereinbelow. First, when the clock pulse .phi..sub.1 arrives with the lines L.sub.3 and L.sub.4 being held at a high and a low potential, carriers are injected from the load transistor Q.sub.1 to the base of the inverter transistor Q.sub.4, thereby to turn the inverter transistor Q.sub.4 on. Carriers which may be injected from the load transistor Q.sub.2 are absorbed by the turned-on inverter transistor Q.sub.4, thereby holding the inverter transistor Q.sub.3 in its turned-off state. If a parasitic capacitance C.sub.1 accompanied by the line L.sub.1 has been charged up, the positive potential of the line L.sub.1 is held as it was. On the other hand, a parasitic capacitance C.sub.2 of the other line L.sub.2 is discharged through the turned-on inverter transistor Q.sub.4 to lower the potential of the line L.sub.2.
Then, when the clock pulse .phi..sub.2 arrives (at this moment the clock pulse .phi..sub.1 is vanished), the inverter transistor Q.sub.4 is turned on and the state of the inverter transistors Q.sub.3 and Q.sub.4 are stored in the parasitic capacitances C.sub.5 and C.sub.6 of the lines L.sub.5 and L.sub.6.
In this way, the master flip-flop MF and the slave flip-flop SF are alternately clocked by the clock pulses .phi..sub.1 and .phi..sub.2, and the information given to the input lines L.sub.3 and L.sub.4 of the register cell are sent out from the output lines L.sub.5 and L.sub.6 of the register at a predetermined timing.
As can be seen from FIG. 3, the master flip-flop MF and the slave flip-flop SF may have the same structure. A structure of the master or slave flip-flop is shown in FIG. 4.
In the figure, an n type semiconductor wafer 110 is formed with an n-type semiconductor substrate 111 of a low resistivity and an n type epitaxial layer 112 of a relatively high resistivity grown on the substrate 111. In the n type epitaxial layer 112, p type regions 113, 114 and 115 of a relatively low resistivity are formed by, for example, the selective diffusion technique. In the p type regions 113 and 115, n type regions 116, 117, 118 and 119 of a low resistivity are formed by, for example, the selective diffusion. Metal electrodes 120, 121, 122, 123, 124, 125 and 126 are formed on the regions 113, 114, 115, 116, 117, 118 and 119, respectively. Another electrode 127 is formed on the lower surface of the n type semiconductor substrate 111. Pairs of the electrodes 120 and 125, and 122 and 124 are connected by metal leads.
Correlation of the structure of FIG. 4 and one flip-flop in the register of FIG. 3 is as follows. Semiconductor regions 112, 113 and 114 constitute the base, the collector and the emitter of the load transistor Q.sub.2, respectively, while the regions 112, 114 and 115 constitute the base, the emitter and the collector of the load transistor Q.sub.1, respectively. The regions 112, 115 and 118 and 119 constitute the emitter, the base and the first and the second collectors of the inverter transistor Q.sub.4, respectively, while the regions 112, 113 and 116 and 117 constitute the emitter, the base and the first and the second collectors of the inverter transistor Q.sub.3, respectively. Here, the n type region 111 is considered as part of the n type region 112.
As can be seen from the above statement, the conventional register cell as described above has similar drawbacks and inconveniences as described above with respect to the memory cell.
Namely, since the load transistors Q.sub.1 and Q.sub.2, which inject carriers to the inverter transistors Q.sub.4 and Q.sub.3 as well as serve as the collector loads for the inverter transistors Q.sub.3 and Q.sub.4, are formed with bipolar transistors, they have an inherently limited switching speed due to the carrier storage effect therein.
Furthermore, since the load transistors Q.sub.1 and Q.sub.2 have lateral structures, it is difficult to reduce the base width W.sub.B thereof, and hence is difficult to increase the carrier injection efficiency .alpha. (equal to the common base current amplifiction factor). Namely, the leak component of the carriers is large and the power loss is large. In particular, when the amount of the injected carriers becomes large, the potential at the collectors 113 and 115 of the injector transistors Q.sub.2 and Q.sub.1 rises to cause the reverse injection therefrom. Furthermore, the pn-junction between the emitter 114 and the base 112 becomes forwardly deeply biased, and hence the effect of the base resistance becomes large. Thus, the rate of the carriers escaping into the semiconductor substrate 111 increases. Therefore, the carrier injection efficiency .alpha. rapidly falls down with an increase in the injection current I.sub.i (the current flowing into the common emitter of the injector transistors Q.sub.1 and Q.sub.2), as shown in FIG. 16.
Furthermore, the conventional register cell should be clocked by applying clock pulse .phi..sub.1 and .phi..sub.2 to the emitters of the injector transistors of the master and the slave flip-flops. Thus, a large power is required for clocking.